1. Field of the Inventions
The invention relates to integrated power driver circuits and in particular to an improved level-shifter for driving the output stage of an integrated power driver.
2. Background Information
In today's environment, class-D amplifiers are used to provide an integrated solution for applications such as powering audio devices. Class-D amplifiers have an advantage in power consumption and size over more traditional analog amplifiers. Generally, they do not require bulky transformers or heat sinks making them more suitable for integrated circuits.
In particular, the class-D amplifier unlike a traditional amplifier produces an output comprising a sequence of pulses. Typically, these pulses vary in width or in density in methods known as pulse width modulation (PWM) or pulse density modulation (PDM). The average value of these pulses represents the instantaneous amplitude of the output signal. These pulses introduce unwanted high-frequency harmonics, which are typically removed by a low pass filter.
FIG. 1 is a block diagram illustrating the typical architecture of class-D amplifier 100. The input signal is converted to pulses using modulator 102 which can be a pulse width modulator or a pulse density modulator. A common implementation of a pulse width modulator uses a high speed comparator to compare the input signal against a triangle wave. The modulated signal is then amplified by amplifier 104 and finally demodulated by low pass filter 106. The demodulated signal can then be used, for example by speaker 108.
Of particular interest in integrated power drivers such as Class-D amplifiers as described above and DC-DC converters are the output stages which typically use a complimentary MOS structure. FIG. 2 is a circuit diagram exemplifying the output stage of a power driver. At the output is a p-type field effect transistor (PFET) 202, also referred to as the high-side switch, and an n-type field effect transistor (NFET) 204, also referred to as the low-side switch, in a complementary structure. Both field effect transistors operate as a switch. When high-side switch 202 is in the ON state and NFET 204 is in the OFF state, the output voltage is pulled up to the VDDH level. When high-side switch 202 is in the OFF state and the NFET 204 is in the ON state, the output voltage is pulled down to the VSSH level. As is typical with PFET switches, the PFET is in the ON state when the gate voltage is at least one PFET threshold below its source and is OFF when the gate-to-source voltage is zero. Similarly, typically with NFET switches, the NFET is in the ON state when the gate voltage is at least one NFET threshold above its source and is OFF when the gate-to-source voltage is zero.
The difficulty arises when the output requirements call for a higher voltage than is typically tolerated by the technology. For example, speaker drivers in PC audio applications must produce an average power of 2.5W on a 4-Ω speaker; therefore a 5V power supply is needed. However, most advanced integration technologies use 0.35 μm or smaller geometries that only produce 3.3V tolerant FET devices. Because the source of high-side switch 202 is tied to the power rail VDDH, the control signal supplied to the gate of high-side switch 202 can only be allowed to drop 3.3V below VDDH; for the case where VDDH is set to 5V, the gate cannot go below 1.7V. Similarly, the control signal supplied to the gate of low-side switch 204 can only be allowed to go 3.3V above VSSH; for the case where VSSH is set to ground (0V), the gate cannot go above 3.3V.
Therefore in order to operate this circuit in this type of environment, level shifter 206 is used to shift a modulated signal so that the swing between the power supply voltage VDDH and the gate of high-side switch 202 never exceeds 3.3V. Additionally, level shifter 206 can also be used to supply the gate voltage to low-side switch 204 such that the swing between the gate and power supply voltage VSSH never exceeds 3.3V.
The level-shift operation should be fast, in particular there should be no significant delays between the signals to high-side switch 202 and low-side switch 204. Any delays between the signals can reduce the performance of the circuit; in class-D amplifiers a delay between the two signals in the output stage causes longer transition periods between the OFF and ON states of the output which produces a degradation in total harmonic distortion (THD).
Also, it is desirable to control the voltage levels at the gates of both high-side switch 202 and low-side switch 204 accurately. Ideally the gate-to-source voltage (VGS) for high-side switch 202 in the ON state should be −3.3V and VGS for low-side switch 204 in the ON state should be 3.3V under all process, voltage, and temperature (PVT) conditions. However, it should not exceed these limits. In particular, variations in supply voltages VDDH and VSSH can be induced by large amounts of current flowing from and into the load which can be problematic. In the case of a class-D amplifier the current can flow in either direction resulting in a significant increase or decrease of supply potentials. For example, if the VSSH potential increases while low-side switch 204 is driven to 3.3V, its effective VGS is reduced resulting in increased resistance in the ON state. The increased resistance can result in requiring a larger FET, an increase in power consumption, a decrease in performance or a combination of all three. If the VSSH potential decreases the low-side switch 204 switch VGS is increased and may exceed the technology limitations causing reliability issues. Similar considerations apply to high-side switch 202 and VDDH variations.
It is important that level shifter 206 be able to maintain a controlled and constant output swing independent of the voltage of the power rails. This is especially challenging in the case of battery-operated systems where the positive power rail voltage can vary substantially depending on battery conditions.
In paper M. Berkhout “An Integrated 200-W Class-D Audio Amplifier”, IEEE JSSC, vol. 38, no. 7, July 2003, an external bootstrap capacitor and an externally-decoupled power rail are used to drive the two power FETS. The bootstrap capacitor must be large compared to the capacitive load given by the high-side FET device, therefore it cannot be integrated. This is undesirable because to include this solution as part of an integrated package, additional pins must be supplied in order to use an external capacitor.
FIG. 3 is a circuit diagram of a known level-shifter for driving the high-side switch. The level-shifter comprises PFET 302 and NFET 308 coupled by a cascode pair, PFET 304 and NFET 306. The cascode pair is coupled to an intermediate voltage VINT, which is typically the average of supply voltages VDDH and VSSH. The output of the level shifter swings between VDDH and VINT+Vthp where Vthp is the threshold voltage for PFET 304. As an example, if VDDH is 5V, VSSH is 0V, and Vthp is 0.8V, VINT is equal to 2.5V and the high-side swing is only 1.7V, which falls short of the desired 3.3V. The suboptimal voltage swing as mentioned above leads to higher power consumption and lower performance by the output stage or requires a larger high-side switch. Even if a typical VINT was chosen to bring the voltage swing closer to the net 3.3V desired, the falling edge of the control signal is slow because for the control signal to go from high to low requires current to flow through three series pull-down elements PFET 304, NFET 306 and NFET 308. Finally, the net voltage swing is highly dependent on the supply voltages. Accordingly, various needs exist in the industry to address the aforementioned deficiencies and inadequacies.